Staff profile

Welcome to my Homepage! I am an Assistant Professor in Computer Science, Durham University (UK) with a multifaceted background that spans both industry and academia. 

I am a Senior Member of IEEE, received my Ph.D. degree in computer science and engineering from the Indian Institute of Technology Guwahati, India, in February 2018. Prior to my joining at Durham University, I worked at Norwegian University of Science and Technology, Trondheim, Norway, as a Postdoctoral Researcher through ERCIM and Marie Curie Individual Fellowships from EU (Jan 2019 - May 2023). I also worked as a Computer System Architect at ZeroPoint Technologies AB, Gothenburg, Sweden (Jun 2022 - May 2024) and as an Assistant Professor in Computer Science and Engineering at Indian Institute of Information Technology Guwahati, India (Jul 2018 - Dec 2018).

My broad area of research is in high-performance computer architecture and compilers, with special focus on non-volatile memory technologies, post-CMOS architecture, thermal management, loop optimisation, etc.  For my publication details, you can visit my DBLP or Google Scholar pages. 

If your research interests align with mine, and you are enthusiastic in doing PhD/Postdoctoral research, we can have a chat. Feel free to reach me at shounak.chakraborty@durham.ac.uk. 

• High Performance Computer Architecture, Energy Efficient Computing, On-chip Thermal Management, Caches & Cores, SoC Design, Non-Volatile Memories, Compilers, Time-Critical Computing

Conference Paper

• MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing
  
  Chakraborty, S., Saha, S., Sjalander, M., & Mcdonald-Maier, K. (2024). MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. In DAC ’24: Proceedings of the 61st ACM/IEEE Design Automation Conference (pp. 1-6). ACM. https://doi.org/10.1145/3649329.3655985
• TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture
  
  Agarwal, S., Chakraborty, S., & Själander, M. (2024). TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. In 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (pp. 852-864). IEEE. https://doi.org/10.1109/ipdps57955.2024.00080
• Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)
  
  Agarwal, S., Chakraborty, S., & Själander, M. (2023). Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). In 2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE. https://doi.org/10.1109/dac56929.2023.10247878
• NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems
  
  Chakraborty, S., Safarpour, M., & Silvén, O. (2023). NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. In Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 33-42). Springer Nature Switzerland. https://doi.org/10.1007/978-3-031-46077-7_3
• STIFF: thermally safe temperature effect inversion aware FinFET based multi-core
  
  Chakraborty, S., Soteriou, V., & Själander, M. (2022). STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. In CF ’22: Proceedings of the 19th ACM International Conference on Computing Frontiers. ACM. https://doi.org/10.1145/3528416.3530223
• RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore
  
  Sharma, Y., Moulik, S., & Chakraborty, S. (2022). RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 608-611). IEEE. https://doi.org/10.23919/date54114.2022.9774647
• ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache
  
  Agarwal, S., & Chakraborty, S. (2021). ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. In 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 171-174). IEEE. https://doi.org/10.1109/asap52443.2021.00032

Journal Article

• HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches
  
  Chakraborty, S., Bunnam, T., Arunruerk, J., Agarwal, S., Yu, S., Shafik, R., & Sjalander, M. (2025). HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Advance online publication. https://doi.org/10.1109/TCAD.2025.3546855
• ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment
  
  Saha, S., Chakraborty, S., Agarwal, S., Själander, M., & McDonald-Maier, K. D. (2024). ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(10), 2944-2957. https://doi.org/10.1109/tcad.2024.3384442
• TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores
  
  Chakraborty, S., Sharma, Y., & Moulik, S. (2024). TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores. ACM Transactions on Embedded Computing Systems, 23(4), Article 61. https://doi.org/10.1145/3665276
• DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore
  
  Saha, S., Chakraborty, S., Agarwal, S., Gangopadhyay, R., Sjalander, M., & McDonald-Maier, K. (2023). DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Transactions on Parallel and Distributed Systems, 34(2), 718-733. https://doi.org/10.1109/tpds.2022.3228751
• ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches
  
  Saha, S., Chakraborty, S., Zhai, X., Ehsan, S., & McDonald-Maier, K. D. (2022). ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(12), 5246-5260. https://doi.org/10.1109/tcad.2022.3161407
• ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms
  
  Sharma, Y., Chakraborty, S., & Moulik, S. (2022). ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms. The Journal of Supercomputing, 78(8), 1-25. https://doi.org/10.1007/s11227-021-04257-7
• WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption
  
  Chakraborty, S., & Själander, M. (2021). WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Transactions on Architecture and Code Optimization, 18(4), Article 55. https://doi.org/10.1145/3471908
• Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization.
  
  Chakraborty, S., Saha, S., Själander, M., & Mcdonald-Maier, K. (2021). Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Transactions on Embedded Computing Systems, 20(5s), Article 62. https://doi.org/10.1145/3476993
• SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems
  
  Moulik, S., Das, Z., Devaraj, R., & Chakraborty, S. (2021). SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems. Journal of Systems Architecture, 114, Article 101953. https://doi.org/10.1016/j.sysarc.2020.101953